smsc sch5617 product preview revision 0.6 (01-09-08) data brief product features sch5617 desktop system controller hub with advanced, 8051c-based auto fan control ? acpi 2.0 compliant ? high performance 8051 ? 2.5x average instruction execution speed improvement over the entire instruction set; i.e., typical 4-clock instruction cycle in high- performance 8051 vs. 12-clock instruction cycle in standard 8051. ? faster clock speed: 32 mhz vs. 16 mhz in standard 8051. ? dual data pointers ? more interrupts: power-fail, external interrupt 2, external interrupt 3, etc. ? a set of external memory/mapped control registers provides the 80c51 core with the ability to directly control many functional blocks of the sch5617. ? 384 bytes of ram as part of the 8051 core ? 4k bytes data ram (869 bytes may be used to patch rom code) ? twelve interrupt sources ? watch dog timer (wdt) ? peci interface ? temperature monitor ? monitoring of up to two remote thermal diodes ? supports temperature readings from -63 degrees to +192 degrees ? supports monitoring of discrete diodes (3904 type diodes) ? supports monitoring substrate diodes (45nm & 65nm processor diodes) ? 1/8th degree temperature resolution ? internal ambient temperature measurement ? limit comparison of all monitored values ? prochot_in# pin ? mapped into temperature monitoring interrupt generation logic ? may be used to adjust fan control limits ? may be configured to force fans on full ? prochot_out pin ? auto-fan control with prochot features ? pwm (pulse width modulation) outputs (3) ? legacy pwm control dc fan outputs ? high frequency pwm options (15khz up to 30khz) ? 2 second delayed start-up for pwm outputs ? fan tachometer or lock rotor inputs (3) ? programmable linear automatic fan control based on temperature ? acoustic enhancement mode ? prochot pins modulate tmin ? fan pwm duty cycle is a function in linear mode of multiple temperatures and prochot signals ? pwm ramp rate closed loop control ? internal ring oscillator for vtr powered logic ? low battery warning ? led control ? smbus isolation logic ? programmable wake-u p event interface ? pc2001 compliant ? general purpose input/output pins (30 host controlled, 16 8051 controlled) ? 21 dedicated scratchpad registers ? isa plug-and-play compatible register set ? system management interrupt ? glue logic ? ide reset/buffered pci reset outputs ? power ok signal generation ? power sequencing ? power supply turn on circuitry ? resume reset signal generation ? hard drive front panel led ? 2.88mb super i/o floppy disk controller ? licensed cmos 765b floppy disk controller ? software and register compatible with smsc's proprietary 82077aa compatible core ? supports two floppy drives ? configurable open drain/push-pull output drivers ? supports vertical recording format ? 16-byte data fifo ? 100% ibm? compatibility ? detects all overrun and underrun conditions ? sophisticated power control circuitry (pcc) including multiple powerdown modes for reduced power consumption ? dma enable logic ? data rate and drive control registers ? 480 addresses, up to eight irqs, and four dma options ? enhanced digital data separator ? 2 mbps, 1 mbps, 500 kbps, 300 kbps, 250 kbps data rates ? programmable pre compensation modes
order number: sch5617-ns for 128 pin, qfp le ad-free rohs compliant package desktop system controller hub with advanced, 8051c-based auto fan control revision 0.6 (01-09-08) 2 smsc sch5617 product preview 80 arkay drive, hauppauge, ny 11788 (631) 435-6000, fax (631) 273-3123 copyright ? 2008 smsc or its subsidiaries. all rights reserved. circuit diagrams and other information relating to smsc products are included as a means of illustrating typical applications. consequently, complete in formation sufficient for construction purposes is not necessarily given. although the information has been checked and is believed to be accurate, no re sponsibility is assumed for inaccuracies. smsc reserves the right to make changes to specifications and product descriptions at any time without notice. contact your local sm sc sales office to obtain the latest specifications before placing your product order. the provision of this information does not convey to the purchaser of the described semicond uctor devices any licenses under any patent rights or other intellectual property rights of smsc or others. all sales are expressly conditional on your agreement to the te rms and conditions of the most recently dated version of smsc's standard terms of sale agreement dated before the date of your order (the "terms of sale agreement"). the pro duct may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. anomaly sheets are availab le upon request. smsc products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. any and all such uses without prior written approval of an officer of smsc and further testing and/or modification will be fully at the risk of the customer. copies of this document or other smsc literature, as well as the terms of sale agreement, may be obtained by visiting smsc?s website at h ttp://www.smsc.com. smsc is a registered trademark of standard microsystems corporat ion (?smsc?). product names and company names are the trademarks of their respective holders. smsc disclaims and excludes any and all warranties, including wi thout limitation any and all implied warranties of merchantabil ity, fitness for a particular purpose, title, an d against infringement and the like, and any and all warranties arising from any cou rse of dealing or usage of trade. in no event shall smsc be liable for any direct, incidental, indire ct, special, punitive, or cons equential damages; or for lost data, profits, savings or revenues of any kind; regardless of the form of action, whether based on contrac t; tort; negligence of smsc or others; strict liability; breach of warranty; or otherwise; whether or not any remedy of buyer is h eld to have failed of its essential purpose, and whether or not smsc has been advised of the possibility of such damages. ? keyboard controller ? 8042 software compatible ? 8 bit microcomputer ? 2k bytes of program rom ? 256 bytes of data ram ? four open drain outputs dedicated for keyboard/mouse interface ? asynchronous access to two data registers and one status register ? supports interrupt and polling access ? 8 bit counter timer ? port 92 support ? fast gate a20 and kreset outputs ? serial ports ? two full function serial ports ? high speed ns16c550a compatible uarts with send/receive 16-byte fifos ? programmable baud rate generator ? supports all standard baud rates up to 115k bps ? supports non-standard baud rates of 230k and 460k bps ? modem control circuitry ? 480 address and 15 irq options ? infrared port ? multi protocol infrared interface ? irda 1.0 compliant ? sharp ask ir ? 480 addresses, up to 15 irq ? multi-mode? parallel port with chiprotect? ? standard mode ibm pc/xt ?, pc/at ? , and ps/2? compatible bi-directional parallel port ? enhanced parallel port (epp) compatible - epp 1.7 and epp 1.9 (ieee 1284 compliant) ? ieee 1284 compliant enhanced capabilities port (ecp) ? chiprotect circuitry for protection ? 960 address, up to 15 irq and four dma options ? lpc interface ? multiplexed command, address and data bus ? serial irq interface compatible with serialized irq support for pci systems ? pme interface ? power good output ? 3.3 volt i/o ? 128 pin qfp, lead-free rohs compliant package
desktop system controller hub with advanced, 8051c-based auto fan control smsc sch5617 3 revision 0.6 (01-09-08) product preview general description the sch5617 is a 3.3v pc 2001 compliant super i/o controller with an lpc interf ace. all legacy drivers used for super i/o components are support ed making this interface transparent to the supporting software. the lpc bus also supports power management, such as wake-up and sleep modes. the sch5617 provides temperature monitoring with auto fan control. the temperature monitor is capable of monitoring two external diodes, one inte rnal ambient temperatur e sensor or retrieving temperatures from external processors that implement the peci interface. this device offers programmable automatic fan control support based on one or more of thes e measured temperatures. there are three pulse width modulation (pwm) outputs with high frequency support as well as three fan tachometer inputs. in addition, there is support for a prochot_in# pin that may be used to generate an interrupt, adjust the programmed temperature limits in the auto fan control logic, or force the pwm outputs on full. there is also a separate prochot_out output pin. the glue logic includes various power management logic including generation of rsmrst# and power ok signal generation. there are also four leds to indicate power status and hard drive activity. also included is smbus isolation logic, which ca n be used to isolate smbus signals during power down modes. the part provides 46 general purpose i/o control pins, which offer flexib ility to the syst em designer. there are 21 scratchpad read/write runtime registers for custom use. the sch5617 incorporates the following super i/o com ponents: a parallel port that is compatible with ibm pc/at architecture, as well as the ieee 1284 epp and ecp; two serial ports that are 16c550a uart compatible; a keyboard/m ouse controller that uses an 8042 micro controller; two floppy controllers, which use smsc's true cmos 765b core ; one infrared port that is irda 1.0 compliant. the true cmos 765b core provides 100% compatibility with ibm pc/xt and pc/at architectures and is software and register compatible with smsc's propr ietary 82077aa core. the part also provides a low battery warning circuit. the sch5617 is acpi 1.0b/2.0 compatible support s multiple low power-down modes. it incorporates sophisticated power control circuitry (pcc), wh ich includes keyboard and mouse wake-up events. the sch5617 supports the isa plug- and-play standard register set (v ersion 1.0a). the i/o address, dma channel and hardware irq of each logica l device in the sch5617 may be reprogrammed through the internal configurati on registers. there are up to 48 0 (960 for standard mode parallel port) i/o address location options, a serialized irq interface, and four dma channels.
desktop system controller hub with advanced, 8051c-based auto fan control revision 0.6 (01-09-08) 4 smsc sch5617 product preview block diagram figure 1 sch5617 block diagram sch5617 (128 qfp) digital data separator with write precom- pensation smc proprietary 82077 compatible vertical floppydisk controller core wdata wclock rclock rdata multi-mode parallel port with chiprotect tm leds internal bus (data, address, and control lines) high-speed 16550a uart port 1 keyboard/mouse 8042 controller high-speed 16550a uart port 2 power mgmt general purpose i/o note 1: this diagram does not show power and ground connections. note 2: functions with "*" are located on multifunctional pins. this diagram is designed to show the various functions available on the chip (not pin layout). clock gen lpc bus interface serial irq glue logic tach1 tach2 tach3 hvss remote1+ remote1- remote2+ remote2- hvtr pwm1 pwm2 pwm3 prochot_in# prochot_out ide_rstdrv#*, pci_rst_sys#* pci_rst_slots#*, ps_on#* pwr_good_3v*, pwrgd_ps, rsmrst#* secondary_hd#* primary_hd#* scsi#* hd_led#* led2* led3* led1* lad[3:0] lframe# ldrq# pci_reset# lpcpd# ser_irq pci_clk io_pme#* io_smi#* pd[7:0] busy,slct,pe error#, ack# strobe#, init# slctin# alf# txd1*,rxd1* cts1#*, rts1#* dsr1#*, dtr1#* dcd1#*, ri1#* txd2*,rxd2* cts2#*, rts2#* dsr2#*, dtr2#* dcd2#*, ri2#* kclk, mclk kdat, mdat, kbdrst#, a20m p12*,p16*,p17* rdata#, wdata# mrt0#, mrt1#*, trk0#, index#,wrtprt#,wgate#, hdsel#,drvden0*, dir#, step#, dskchg#,ds0#, ds1#* 8051 analog interface analog block auto fan control rom 14.318 mhz peci interface smbus isolation circuits sclk*, sdat* sclk_1*, sdat_1* peci v ref peci io peci ready gp10*, gp11*, gp15*, gp21*, gp22*, gp23*, gp25*, gp26*, gp31*, gp33*, gp35*, gp36*, gp37*, gp40*, gp41*, gp42*, gp52*, gp53*, gp55*, gp57*, go60*, gp61*, gp75*, gp76*, gp77*, gp80*, gp81*, gp82, gp83*, gp84*, gp8051_[12:1]*, gp8051_[17:14]* runtime registers
desktop system controller hub with advanced, 8051c-based auto fan control revision 0.6 (01-09-08) 5 smsc sch5617 product preview package outline figure 2 128-pin qfp package outline (3.9mm footprint) std compliance interpret dim and tol per asme y14.5m - 1994 dwg number print with "scale to fit" do not scale drawing material finish approved checked drawn scale sheet rev 80 arkay drive hauppauge, ny 11788 usa angular unles s otherwi se specified dimensi ons are in mill imeters and tolerances are: decimal x.x x.xx x.xxx third angle projection name date title revision date description revision history released by jedec: mo-112 (b) & ms-029 (a) package outline 1:1 - - s.k.iliev s.k.iliev s.k.iliev 11/30/04 11/30/04 11/30/04 128 qfp-14x20x2.7mm body-3.9mm footprint mo-128 qfp-14x20-3.9fp - c 1 0.1 0.05 0.025 see detail "a" seating plane notes: 1. all dimensions are in millimeter. 2. tolerance of the true position of the leads is 0.04mm maximum. 3. package body dimensions "d1" and "e1" do not include mold protrusions. maximum mold protrusion is 0.25 mm. 4. dimension "l" is measured at the gauge plane, 0.25mm above the seating plane. 5. details on pin 1 identifier are optional but must be located within the zone indicated. a2 c 3-d view side view a1 a ccc c c d1 d e1/4 e1 3 d1/4 e e top view 5 b 2 3 - see spec front page for revision history -- r2 l1 detail "a" (scale: 3/1) 0.25 0-7 gauge plane l 4 r1
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